The present invention relates generally to data caching, and more particularly, to improved prefetch data caching through iterative feedback.
In computing, a cache is a hardware or software component that stores data so future requests for data can be served faster. A cache is made up of a pool of entries. Each entry has associated data, which may be the result of an earlier computation or the duplicate of data stored in a backing store. Each entry has a tag, which specifies the identity of the data in the backing store of which the entry is a copy. When a cache client (processor) needs to access data in the backing store, it first checks the cache. If an entry can be found in the cache with a tag matching the desired data (cache hit), the data in the cache is used instead of the data in the backing store. When the cache client cannot find an entry in the cache (i.e., the cache does not contain data with the desired tag), the cache client obtains the data (uncached data) from the backing store. A “cache hit” occurs when the cache client can find the requested data in the cache. Conversely, a “cache miss” occurs when data requested by the cache client cannot be found in the cache. The more data requests that can be served from the cache, the faster a processor performs.
A “prefetch” refers to a technique used by computer processors wherein instructions and/or data are fetched by the computer processors before they are needed during a process. A “data cache block touch” refers to processor instructions that can be used to request certain data that the computer processor is likely to use soon. Some processors support load-store instructions that imply cache hints, which are suggestions regarding a data block that will most likely be necessary soon (during processing), and should therefore be loaded into the cache beforehand (i.e., before they are actually needed).
A data stream control register (DSCR) is a special purpose register designed to provide a means to supply information and controls to a prefetch mechanism and to control prefetch settings. In one example, a DSCR has 64 bits. If the DSCR is enabled for any of its transient bits, these bits give hints to the prefetch engine that accesses are likely to be short. Other count bits are used to change the default number of units in either software or hardware streams. A depth attainment urgency field specifies how quickly the hardware-detected stream's depth can be reached. In one example, the depth attainment urgency field accepts values 0-7 that indicate one of the available urgency profiles, such as “default”, “not urgent”, “least urgent”, “less urgent”, “medium urgent”, “more urgent” and “most urgent”. Using the same example, a prefetch stream depth field accepts values 0-7 which correspond to one of the available profiles, such as “default”, “none”, “shallowest”, “shallow”, “medium”, “deep”, “deeper”, and “deepest”. In its deepest state, a prefetch mechanism can grab the most data on a particular pathway. In its shallowest state, the prefetch mechanism can grab the most data from a plurality of different pathways.